1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to electronic component packaging.
2. Description of the Related Art
As the density and complexity of integrated circuit devices increases and the size of such devices shrinks, significant challenges are posed in the design and packaging of these devices. One challenge is that more and more power and signal lines must be electrically connected to the integrated circuit die as the circuit complexity increases, though there is less and less space to allow for such connection as the device sizes shrink. Another challenge is that the conventional approaches for electrically connecting signal and power to the integrated circuit die—such as bonding lead-on-chip (LOC) or tape automated bonding (TAB) leadframe conductors to the die area—are simply not a viable solution for connecting the number of signal and power lines required by today's devices, given the relatively large and unwieldy size of such conductors in comparison to the die size. Such conventional approaches also present packaging challenges in protecting the integrated circuit die from structural or mechanical damage, such as can be caused by moisture or other environmental exposure when leadframe conductors extend through the protective packaging in order to make electrical contact to the outside world.
The electronics industry has attempted to increase the density of die contacts as the number of signal and power lines has increased by using wirebond connection techniques, and has also adopted new types of packaging—such as the ball grid array (BGA), the land grid array (LGA), and the pin grid array (PGA) packages—in order to provide improved device protection and to reduce the package profile. However, these wirebond packaging solutions very often deliver power unevenly to the entire die since the power lines are wirebonded to peripheral bonding pads arrayed on all sides of the active or face surface 23 of the die 22, as illustrated in FIGS. 1 and 2. In particular, FIG. 1 depicts in simplified schematic form a cross-sectional view of a conventional wirebonded BGA package device 10 in which an integrated circuit die 22 (having a back surface 21 and active surface 23) is mounted or attached to a carrier substrate 12 and encased in an insulating package body 20. The solder balls are affixed to a lower surface of the carrier substrate 12 using a solder ball mounting layer 8 which physically attaches and electrically connects each solder ball to a conductive circuit in the carrier substrate. In the package 10, a first reference voltage (e.g., Vss) is supplied to the back surface 21 of the die 22 through electrically conductive paths, such as the VSS/thermal solder ball array 5 and the conductive traces 16. In addition, a second reference voltage (e.g., VDD) is supplied to a peripheral edge of the active surface 23 of the die 22 through electrically conductive paths, such as the VDD solder ball(s) 3, conductive trace(s) 13, vias 14, contact pad 15 and VDD wirebond conductor(s) 24. Lastly, signal information 2 applied to the signal solder balls 1 is electrically connected to a peripheral edge of the active surface 23 of the die 22 through electrically conductive paths, such as wires, contact pads or layers, conductive vias, conductive traces (not shown) formed in a carrier substrate 12 and the signal wirebond conductor(s) 26. In addition to the electrical connection through the back surface 21 of the die 22, VSS information 6 applied to the VSS solder balls 5 is electrically connected to a peripheral edge of the active surface 23 of the die 22 through electrically conductive paths, such as wires, contact pads or layers, conductive vias, conductive traces formed in a carrier substrate 12 and the VSS wirebond conductor(s) (not shown).
With the VDD wirebond conductor(s) 24 being affixed to bonding pads at the periphery of the die 22, power is not delivered uniformly across the active surface 23 of the die 22. This may be illustrated with reference to FIG. 2 which depicts a simplified plan view of the package device 10 depicted in FIG. 1 in which the power or voltage supplied at a central region 27 and/or interior region 28 is reduced as compared to the power or voltage supplied at the peripheral region 29. The voltage drop or power sag in the interior regions 27, 28 results from the fact that the voltage is strongest in the peripheral region 29 where the VDD wirebond conductor(s) 24 are connected to the die 22. The problem of power loss can be especially acute with low power devices using conventional wirebond packaging. For example, with products in the 5-8 watt range, every milli-volt of voltage degradation over the area of a particular power domain can result in performance and/or yield loss. Such voltage drops can impair the performance of high speed CMOS digital logic (e.g., above 600 Mhz) located in areas that are more than approximately 2 mm from a package level supply terminal. Though flip-chip packaging can provide excellent power distribution, its costs are usually higher than wire bond packages and can limit its application space.
Accordingly, there exists a need for an array packaging scheme that provides improved power distribution for an integrated circuit die having multiple signal and power lines. In addition, there is a need for a cost effective semiconductor device package that electrically connects signal and power lines to an integrated circuit die without impairing device performance or yield. There is also a need for improved packaging processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.